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Epson Develops Frame Buffer Embedded Digital Video Encoder For NTSC and PAL Syst

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Epson Develops Frame Buffer Embedded Digital Video Encoder For NTSC and PAL Systems

– TOKYO, Japan, October 30, 2006 –

Seiko Epson Corporation ("Epson") has announced the S1D13771 digital video encoder LSI. The new product can easily be added to digital video systems and was created in response to demand for TV output from embedded products. With a built-in display buffer, high-performance DAC, and high-quality scalar providing bi-cubic input/output scaling, the S1D13771 enables the production of high-quality TV output with low material cost. Production is planned to start from January 2007.

A high-quality internal scaling algorithm and complex TV filters allow for VGA resolution input to be stored using a minimum amount of memory, while providing smoothly scaled output to the full resolution specified by either PAL or NTSC standards. The S1D13771 features wafer level CSP (WCSP), 4.46 x 4.46 mm (ball pitch 0.5 mm), the smallest solution suitable for mobile applications.

While conventional video encoding LSI’s have to get digital video data compliant with ITU-R BT656 or ITU-R BT 601 standards, the S1D13771 is connected directly to the system bus and LCD interface. It can be added-on to a variety of systems regardless of CPU type to easily achieve TV output functions.

Epson regards the embedded market as an important target for its products. The company plans to further boost its lineup to meet customer needs in this promising field.

Product Features

  1. Integrated frame buffer
    -Embedded SRAM
  2. CPU interface
    – 8-bit parallel indirect interface (Intel(R) 80 type)
    – Interface voltage level (3.3 V to 1.8 V typical.)
  3. Input formats
    – RGB 8:8:8, 6:6:6, 5:6:5
    – YUV 4:2:2
    – All input data is processed by the scalar and stored to the frame buffer
  4. TV output
    – Composite PAL/NTSC output
  5. Display function
    – Bi-cubic output scalar for scale-up or scale-down
    – Auto-border/auto-center
    – 15-tap programmable chrominance/luminance filters
    – TV connect/disconnect detection
  6. Miscellaneous
    – System clock: 18 MHz to 27 MHz typical. (PLL integrated)
    – Supply voltage (typical): Core VDD 1.5 V, IO VDD 1.8 V to 3.3 V, DAC VCC 3.0 V
    – Package: W-CSP (4.46 x 4.46 mm), ball pitch 0.5 mm
    – Operating temperature: – 40°C to 85°C

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