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New Epson Application Processor Featuring Built-in MP3 Hardware Accelerator Comb



New Epson Application Processor Featuring Built-in MP3 Hardware Accelerator Combines Advanced Functionality and Low Power Consumption

– TOKYO, Japan, December 11, 2006 –

Seiko Epson Corporation ("Epson") has developed an application processor, the S1C33E08, ideally suited to portable devices such as educational devices, MP3 players, and electronic dictionaries with sound functions, that require high-level data processing, sound processing and displays.

This product offers a one-chip solution integrating functions required for electronic dictionaries, e-books and other portable display devices, such as a color LCD control circuit, USB 2.0 device connectivity, MP3 hardware accelerator, and interfaces for electronic media, SDRAM, and NAND flash memory.

Product features
In addition to the functions of the S1C33E07 application processor released in May 2006, the S1C33E08 features an MP3 hardware accelerator. The accelerator’s built-in MP3 decoder and playback API offer high-speed processing for easy MP3 playback.

The color LCD control circuit is compatible with both STN-type and TFT-type liquid crystal displays and, depending on the hardware, can accommodate accelerators to support features such as Picture in Picture. This enables users of the chip to achieve advanced image capabilities with a minimum of development work.

Power consumption during operation has been reduced by changing the frequency division ratio of the CPU clock and controlling clocks for each block of functions. In addition, Epson’s unique low-leak technology minimizes power leakage in sleep mode.

This new application processor offers the high level of functional integration demanded by electronic dictionaries and e-books combined with longer than ever battery life.

Shipment of samples will begin in December 2006, and volume production is scheduled to start in February 2007. The product will be shipped in bare chip, TQFP, and BGA package versions, and full-scale production is expected to be 1 million units per month.

Epson will continue to expand its lineup of devices featuring low-power technology in response to customers’ diverse needs for such products.

General specifications

Model S1C33E08
Core CPU S1C33000 RISC PE core
Main clock/Sub clock 60 MHz (Max.)/32.768 KHz (Typ.)
CPU (45 MHz)/SDRAM (90 MHz) possible depending on settings
Built-in ROM
Built-in RAM 8 Kbyte
Display RAM 12 Kbyte
(When VRAM is not used, can also be used as internal RAM)
IDMA RAM 2 Kbyte
LCD controller STN/TFT Interface (HR Generic)
Maximum resolution: 320 x 240 (IVRAM only 1bpp display)
Picture in Picture function
USB function controller Supports USB 2.0 full speed mode (12 Mbps)
FIFO 1 Kbyte
(4 general-purpose endpoints + control)
MP3 accelerator MP3 decoder, playback API
Playback rate
Sampling frequency: 48 kHz (max.)
Bit rate: 320 kbps (max.)
Channels: Monaural/stereo
SDRAM controller Supports SDRAM clock up to max. 90 MHz
ADC Successive approximation 10 bit: 5ch
Timer 16 bit (PWM): 6ch, WDT (1ch)
RTC: 1ch
External interface FIFO SIO: 3ch (1ch is compatible with ISO7816)
DMAC High-speed: 4ch Intelligent: 128ch
External bus controller Address bus: 25 bit
Data bus: 8 or 16 bit (selectable)
I/O ports Input/output: 74
Boot functions 8/16-bit external ROM
SPI external Serial Flash ROM
NAND Flash
Supply voltage Core: 1.8 V (typ.)
I/O: 3.3 V (typ.)
Power consumption Sleep mode: 5.5 µW (typ.)
Halt mode: 4 mW (typ.)
MP3 playback: 88 mW (typ.)
Shipping states Bare chip (90 µm pitch)
TQFP24-144 (0.4 mm pitch)
PFBGA-180 (0.8mm pitch)

Related information
Press release: New Epson Application Processor for Electronic Dictionaries and e-Books Combines Advanced Functionality and Low Power Consumption

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